1. Field of the Invention
The present invention relates in general to quadrature amplitude modulation (QAM) receivers, and in particular to an apparatus for providing gain, carrier recovery and equalization for a QAM receiver.
2. Description of Related Art
FIG. 1 depicts a prior art quadrature amplitude modulation (QAM) communication system 6 including a transmitter 8 for converting an input bit sequence (DATA) into a QAM modulated analog signal AQAM, a communication channel 9 for delivering the AQAM signal as an input signal BQAM to a receiver 10. The BQAM signal differs to some extent from the AQAM signal because channel 9 causes some signal distortion and attenuation. Receiver 10 converts the BQAM signal back into the DATA bit sequence. The AQAM signal includes two modulated sinusoidal carriers 90 degrees out of phase with one another, and although the carriers occupy the same frequency band, transmitter 8 and receiver 10 can independently modulate and demodulate the two carriers. QAM system 6 can therefore transmit data at twice the rate of standard pulse amplitude modulation (PAM) system without any degradation in bit error rate.
Transmitter 8 includes a QAM mapping circuit 12 for converting the DATA bit sequence into two symbol sequences In and Qn. Root Nyquist and interpolation filters 14 pulse shape the In and Qn symbol sequences to achieve output sequences I′n and Q′n having good spectral efficiency. A quadrature modulator (QM) 18 then quadrature modulates the output sequences I′n and Q′n of filters 14 to produce data sequences representing the two modulated carrier signals, a summer 20 sums them to form a single sequence representing AQAM, and a digital-to-analog converter (DAC) 21 and a low pass filter 22 convert that sequence into the AQAM signal.
Receiver 10 includes a programmable gain amplifier (PGA) 25 for amplifying the BQAM signal with a gain controlled by an automatic gain control (AGC) circuit 24 to adjust the signal level to the working range of a subsequent analog-to-digital converter (ADC) 26. A low pass filter 27 filters the output of PGA 25 and an ADC 26 digitizes the output of low pass filter 27 to produce a sequence of data elements wn, wherein each nth element wn represents the nth sample of the analog signal output of low pass filter 27. A quadrature demodulator (QDM) 28 then demodulates sequence wn by multiplying it by two sine wave sequences 90 degrees out of phase with one another to produce two sequences of data elements vIn and vQn. Decimation and root Nyquist filters 30 decimate and filter sequences vIn and vQn to produce symbol sequences rIn and rQn having the same symbol rate as the In and θn sequences produced by the transmitter's QAM mapping circuit 12.
A feed forward equalizer (FFE) 32 filters the rIn and rQn sequences to remove inter symbol interference (ISI) due to distortions caused by channel 9 and to finely adjust the sampling phase of the signal, thereby producing “soft decision” symbol sequences yIn and yQn. Each symbol of the yIn and yQn soft decision sequences has more bits than a corresponding symbol of the original In and Qn sequences generated by the transmitter's QAM mapping circuit 12 but represents approximately the same value. A pair of slicers 34 convert the soft decision sequence into lower resolution “hard decision” sequences aIn and aQn matching the In and Qn symbol sequence outputs of QAM mapping circuit 12. A QAM de-mapping circuit 36 converts the aIn and aQn symbol sequences into the output DATA sequence.
FIG. 2 depicts a portion of QAM receiver 10 of FIG. 1 in a more compact form wherein sequences vIn and vQn of FIG. 1 are represented by single complex sequence vn=vIn+jvQn. Similarly, rn=rIn+jrQn, yn=yIn+jYQn, and an=aIn+jaQn.
FIG. 3 is a more 1 CLK produced by a timing recovery circuit 39 which adjusts the frequency of the CLK signal to as nearly as possible match the transmitter's output symbol rate.
The receiver's quadrature demodulator 28 of FIG. 2 includes a pair of multipliers 41 (only one is shown in FIG. 3) for multiplying the wn sequence by two carrier sequences produced by a direct digital frequency synthesizer (DDFS) 43 to produce complex sequence vn=vIn+jQn wherevIn=wn[cos(ωtn+θn)], andvQn=wn[−sin(ωtn+θn)].The carrier sequences mimic the behavior of the two carrier signals that are 90 degrees out of phase with one another. A carrier recovery system 42 supplies DDFS 43 with input data θn for controlling the quadrature demodulation phase angle of the carrier sequences.
Feed forward equalizer 32 of FIG. 2 includes a complex finite impulse response (FIR) filter 44 for filtering the rn sequence to produce the soft decision yn sequence. Each symbol of the yn sequence is a weighted sum of preceding and subsequent samples of the rn sequence, with weighting being determined by a set of filter coefficients f supplied as input to FIR filter 44 by an FFE adaptation circuit 46. FFE adaptation circuit 46 adjusts filter coefficients f as necessary to remove inter symbol interference (ISI) due to channel distortions and to finely adjust sampling phase.
FIG. 4 depicts a version of a QAM receiver that is generally similar to that of FIG. 3 except that in FIG. 4, DDFS 43 operates with a phase angle rotating at a fixed rate, and a pair of multipliers 45 multiply the complex output sequence of FIR filter 44 by a complex sequence based on en to remove the carrier components from yn.
Referring to FIG. 3, for receiver 10 to produce a hard decision sequence an correctly representing the In and Qn output sequences of the transmitter's QAM mapping circuit 12 (FIG. 1), all of control circuits 24, 42 and 46 must appropriately adjust their output control data values G, θn and f, and timing recovery circuit 39 must appropriately adjust the frequency of clock signal CLK. Control circuits 24, 42 and 46 monitor various characteristics of, or relationships between, the various symbol sequences receiver 10 produces and adapt their control data outputs so that the symbol sequences exhibit the desired characteristics or relationships. On system start up, the values of control data G, θn and f and the frequency of the CLK signal will be incorrect, and the complex output hard decision sequence an will not correctly reflect the In and Qn sequences generated by the transmitters QAM mapping circuit 12 (FIG. 1). However after receiver 10 begins to process an incoming BQAM signal, control circuits 24, 39, 42 and 46 adjust their outputs so that the an sequence correctly represents the original In and Qn sequences.
Since the goal of control circuits 24, 39, 42 and 46 is to ensure that receiver 10 produces correctly valued hard and soft decision symbols, then the control circuits can most accurately determine how to adjust their output by monitoring aspects of the hard and/or soft decision sequences yn and an. However since values of yn and an are affected by how well each of the control circuits adjust its output, it is necessary to carefully coordinate the algorithms employed by control circuits 24, 39, 42 and 46 so that they form a stable control system in which all control outputs converge to correct values.
The various prior art algorithms that FFE adaptation circuit 46 may use when establishing values of FFE coefficients f can be classified as decision directed (DD) or non decision directed (NDD). DD algorithms are more accurate than NDD algorithms, but a DD algorithm may not converge unless values G and θn, and the frequency of the CLK are nearly correct before the DD algorithm will be able to converge on correct FFE filter coefficient values. NDD algorithms are less accurate than DD algorithms, but some NDD algorithms can converge regardless of the value of θn, provided that gain control data G and CLK signal frequency are nearly correct. A prior art FFE adaptation circuit 46 may initially operate in an NDD adaptation mode following system startup, employing an NDD algorithm to coarsely adjust the FFE filter coefficient values. After carrier recovery circuit 42 then coarsely adjusts θn, the FFE adaptation circuit 46 begins operating in a DD mode, employing a DD algorithm to finely adjust the FFE filter coefficient values.
Depending on the NDD algorithm employed, the ability of FFE adaptation circuit 46 to coarsely adjust filter coefficients f can depend to some extent on how well carrier recovery circuit 42 currently estimates θn. Conversely, the ability of carrier recovery circuit 42 to coarsely adjust θn depends on how well FFE adaptation circuit 46 has coarsely adjusted equalization filter coefficients f. To resolve this interdependence problem many prior art FFE adaptation circuit 46 employ a “constant modulus” algorithm (CMA) to coarsely adjust f during the NDD mode because the CMA algorithm enables the FFE adaptation circuit to coarsely adjust FFE coefficients f regardless of whether carrier recovery circuit 42 has properly adjusted θn, provided that the magnitude of G and the CLK signal frequency are approximately correct. The following is an example of how the control circuits of prior art receiver 10 adjust G, θn, f and CLK signal frequency:
1. AGC 25 monitors wn and coarsely adjusts G.
2. Timing recovery circuit 39 adjusts the CLK signal to a fixed frequency matching the expected symbol rate of the VQAM signal.
3. After AGC 25 has coarsely adjusted gain G, FFE adaptation circuit 46, employing a CMA NDD algorithm, is able to coarsely adjust FFE filter coefficients f.
4. After FFE filter coefficients f are coarsely adjusted, carrier recovery circuit 42 is able to coarsely adjust θn.
5. With G, θn, f and CLK coarsely adjusted, yn and an will be nearly correct. FFE adaptation circuit 46 then begins employing a DD algorithm.
6. AGC controller 36 and timing recovery circuit 39 may begin monitoring yn and/or an instead of wn so that they can more accurately adjust gain G and CLK signal frequency.
7. As G, f and CLK are more finely adjusted, the algorithm employed by carrier recovery circuit 42 is able to more finely adjust θn.
One problem with using the CMA algorithm for coarse equalization adaptation is that a circuit implementing a CMA algorithm requires many expensive multipliers. A reduced constellation algorithm (RCA) requires fewer multipliers to implement, but is not reliable for use in the coarse adjustment phase because it cannot correctly adjust coefficient values until θn is nearly correct. What is needed is a less expensive system for providing gain, carrier recovery and equalization for a QAM receiver that does not require the use of a CMA FFE adaptation algorithm during the coarse adjustment phase.